The present invention concerns a lateral double-diffused insulated gate field effect transistor where the extended drain region is a parallel combination of a single-sided junction field effect transistor (JFET) and a double-sided JFET. The present invention also relates to the construction of a bipolar transistor with an extended collector region. The present invention additionally relates generally to how metal-oxide-silicon (MOS) and/or a bipolar transistors can be effectively shielded from a substrate in a classic junction isolated technology.
Thin layer (resurfed) lateral double diffused metal oxide silicon (D-MOS) transistors have been shown to be an efficient means to integrate high voltage devices in the same die as low voltage control functions. See, for example, Sel Colak Effects of Drift Region Parameters on the Static Properties of Power LDMOS, IEE Transactions on Electron Devices, VOL. ED-28, No. 12, pp. 1455-1466 (December 1981). This reference describes a device which can be considered a series combination of a D-MOS transistor and a single-sided JFET. The single-sided JFET functions as a pinch resistor. The JFET is commonly a thin n-type epitaxial layer deposited on top of a p-type substrate.
In order to improve thin layer lateral D-MOS transistors as a source follower and further reduce resistance when the device is "on", a surface layer of p-type doping has been added. The modified device can be considered a D-MOS transistor in series with a double-sided JFET. See for example, A. W. Ludikhuize, High-Voltage DMOS and PMOS in Analog IC's, IEDM, pp. 81-84 (1982).
An efficient and simplistic way to incorporate a thin layer lateral high voltage MOS transistor which constitutes a series combination of a normal MOS transistor (not D-MOS) and a double-sided JFET is described in U.S. Pat. No. 4,811,075 issued to Klas H. Eklund for High Voltage MOS Transistors.
In another proposed device in the prior art, a thin layer lateral D-MOS transistor is in series with a single-sided JFET and with a parallel arrangement of a single-sided JFET and a double-sided JFET. This device utilizes three epitaxial layer to improve the device as a source follower. See U.S. Pat. No. 4,626,879 issued to Sel Colak for Lateral Double-Diffused MOS Transistor Devices Suitable for Source-Follower Applications.
For these and similar devices, it is very often necessary to provide some shielding in order to allow operation in high voltage applications.